High performance fractional-N PLLs are commonly employed in wireless transceiver applications to drive clocks into transmit and receive RF mixers. These PLLs generate flexible frequency low phase noise RF clocks with low spurious content through fractional-N PLL multiplication of a lower frequency reference clock. These PLLs are termed “fractional-N” because they are capable of generating output frequencies through frequency multiplication of a reference frequency signal, and a multiplication factor (N) can take both integer values and non-integer or fractional values.
Wireless transceivers, particularly in cellular or mobile RF applications, are often highly sensitive to spectral pollution (or spurious content) on their RF clock signals. If there is unwanted spurious content in the RF clock signal, the spurious content will cause spectral pollution of the mixer output signal. Because RF transceivers typically operate on a set of pre-defined RF frequencies or channels, these fractional-N PLLs typically need to be capable of generating a specific set of pre-defined RF clock frequencies with regular spacing (commonly 100 kHz). Each RF clock frequency must have minimal spectral pollution, including at offsets as low as 100 kHz, because, for example, content on the RF clock signal at 100 kHz causes unwanted interaction in the signal path between content on neighboring channels (channels that are separated by 100 kHz spacing).
A common challenge in RF clock generation is that for specific RF channels, the RF clock generated from a fractional-N PLL has unacceptable spectral pollution. The problematic RF clock frequencies are frequencies where the RF clock frequency is very close to an integer multiple of the reference clock frequency. Numerous effects in a highly integrated device could cause poor behavior in these scenarios. For example, when an voltage controlled oscillator built using a parallel inductance-capacitance resonant circuit (LC VCO) is tuned by a fractional-N PLL loop to resonate near to an integer multiple of the reference clock, it is possible for harmonics of the reference clock switching activity (present inside the integrated device) to cause ripple or movement in shared power or ground connections. The VCO circuit is uniquely sensitive to the harmonic frequency of the reference clock that is very close to the VCO's resonant frequency. Coupling directly into the VCO of this particular reference clock harmonic can cause spectral pollution for these specific configurations.
Conventional ways of mitigating spectral pollution include ensuring VCO isolation in relation to reference switching circuitry, using dedicated power domains and large spacing between circuits. This increases cost in a highly integrated circuit.
Another cause of problematic behavior for this type of RF clock frequency configuration is that the inherent quantization noise of delta sigma modulator (DSM) fractional-N phase modulation sequence can be unacceptably high. For near-integer configurations it is possible for the inherent quantization noise of a non-randomized DSM to have too much power concentrated at a specific low offset frequency (for example, where the PLL's low pass characteristic will not provide attenuation). To mitigate this, the DSM architecture is chosen such that this effect is at an acceptable level. Typically a higher order DSM is employed to ensure that the inherent quantization noise in the DSM output signal is sufficiently minimized at lower frequencies where the PLL provides minimal filtering.
An additional concern with conventional systems is the non-linear nature of the PLL's phase detection and charge pump circuitry. The choice of higher order DSMs in conventional systems may reduce the power in low frequency quantization noise, but also increases the power in higher frequency harmonics of the repetitive quantization noise sequence generated by the DSM activity. Before the PLL can perform its low-pass characteristic on DSM quantization noise, the quantization noise signal must pass through the non-linear phase detection and charge pump response. This non-linearity introduces folding of the quantization noise (also known as intermodulation) where some of this intermodulation power will fall at lower frequencies. Intermodulation falling at low frequencies will experience little or no filtering by the PLL's low pass characteristic.
Conventional strategies for mitigating the non-linear characteristic of the phase detection and charge pump circuitry include introducing a static phase shift between the arrival of the reference clock and feedback clock at steady state. This static phase shift can be performed, for example, in a charge pump PLL by introducing an offset current into the loop filter. Conventional techniques generally introduce some noise (due to noise of the offset current or the additional noise injected during the offset-correcting current pulse) and also introduce a single frequency phase modulation tone at the reference clock rate due to the loop filter ripple associated with this activity.
Alternatively, significant conventional system efforts can be taken to match and balance the up and down currents in the charge pump and significant system effort can be made to provide isolation between the switching currents associated with the arrival of feedback clock edges and reference clock edges in an attempt to ensure that the phase detection circuit and charge pumping activity is maximally linear both near the zero phase offset point and at larger positive and negative phase differences. Optimizing these characteristics is a standard part of appropriate fractional-N PLL circuit design efforts. Even with best efforts to achieve sufficient linearity, non-idealities remain in conventional circuits that introduce non-linearity. In stringent applications, it may be challenging to achieve the necessary linearity performance through circuit design efforts alone.
Efforts can be taken to randomize or whiten the quantization noise spectrum from the DSM. These activities can help to avoid the quantization noise from folding through the non-linearity to create power in a concentrated set of intermodulation tones in low frequency bins. Whether the quantization noise generated by the DSM is repetitive (i.e. made up of many discrete tones) or whitened (i.e. spread smoothly across a range of frequencies), the quantization noise will experience intermodulation in both cases and produce some significant power at low offset frequencies where the PLL provides minimal attenuation.
Conventional high-performance fractional-N RF clock generators that target applications with stringent restrictions on spurious pollution of RF clock signals (e.g. cellular/mobile RF transceivers) typically employ brute force approaches to solving high spurious content for near-integer multiplier Fractional-N PLL configurations. System effort is employed in order to produce optimally linear PLL circuits (with most effort being required in phase detector and charge pump design). Also additional circuit techniques are often enabled when the device must operate at these frequencies, which allow spurious content to be reduced but often along with significant additional clock signal impairments (such as significant additional phase noise due to the broadband dithering activity used to break up fractional-N tonal behavior). Conventional broadband dithering techniques employ rational fractions as frequency for PLLs across many frequencies and add other content to the reference frequency. Where broadband tones are dithered across a range of frequencies the tone often mixes with itself and is not well filtered. This smearing of the input signal creates an intermodulation affect which causes further problems with using the signal.
In certain cases, users of conventional devices may simply choose to accept that performance is unacceptable in these near-integer frequencies and spend resources elsewhere in the RF transceiver to make up for the fact that the RF clock is unable to operate with acceptable performance at certain frequencies.
It is desirable to find alternative ways to reduce high spurious content occurring in near-integer multiplier PLL configurations using methods that reduce the negative impacts of the existing approaches. It is, therefore, desirable to provide a method and an apparatus for reducing spectral pollution.